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The gate bias voltage V Bias for the NMOS transistors needs to be a voltage level within the low voltage domain and defines by the appr. Usually V Bias can be easily choosen as being of the same voltage level as the low voltage domain supply level. Said drain of said NMOS transistors is equally fabricated with an extended drain design.

Looking back again, at that voltage domain separation line in FIG. Extended drain design for CMOS transistors signifies in that context, that the common, for source and drain substantially symmetrical layout of CMOS devices, fabricated with a standard CMOS process, is modified in such a way, that now between gate and drain an extra space, covered with additional field oxide is introduced. This type of transistor therefore is now substantially unsymmetrical.

These are values currently achievable by semiconductor foundries; it may be noted, that these values are strongly depending on the CMOS feature size. It is evident, that the extra masks and fabrication steps for extended drain devices are influencing the cost of production. The reference signal is therefore proportional to the high voltage supply V HV but could also be an absolute reference level.

For clarification, the terms low and high voltage domain are now defined more precisely. The voltages for powering said logic circuit blocks in the low voltage domain come from a low voltage supply, usually named as V DD common supply voltages of todays CMOS technologies. The high voltage domain is connected to said supply voltage V HV ,—of ranges e. The voltage indication V SS signifies ground potential. All the ground terminals of the circuit are connected to that voltage V ss. As a first step is described, how to transform the static high-voltage supply levels into static supply currents; for the signal input and the reference in put branch correspondingly.

With step the high-voltage input signal is then transformed into proportional current signal. In step said static supply currents and said input signal current are then combined into resulting current input signals; again for each branch respectively. Step feeds said current signals into the current comparator block, which is operating in low-voltage domain; always handling each branch accordingly.

Within step the comparison of said current signals within the current comparator operating in low-voltage domain is effected. Finally in step , the wanted output signal is generated, which describes now completely in the low-voltage domain the mutual relations of the input signals from the high-voltage domain. As shown in the preferred embodiments, this novel circuit provides an effective and manufacturable alternative to the prior art.

While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention. Effective date : Year of fee payment : 4. Year of fee payment : 8. Year of fee payment : A circuit and method are given, to realize a high voltage comparator, which generates an output signal for follow-up processing in the low-voltage domain.

The high-voltage comparison task is essentially replaced by a current comparison, implemented as a combination of a voltage to current transforming stage with a CMOS current comparator circuit, where only very few parts are working in the high voltage domain. Using the intrinsic advantages of that solution the circuit of the invention is manufactured with standard CMOS technology and only four discrete or integrated extended drain MOS components at low cost. This solution reduces the complexity of the circuit and in consequence also power consumption and manufacturing cost.

What is claimed is: 1. A method for realizing a high voltage comparator comprising:. The method according to claim 1 wherein said step of transforming the static high voltage supply levels into the static currents is implemented using a resistor. The method according to claim 1 wherein said step of transforming the static high voltage supply levels into the static currents is implemented using an equivalent resistor circuit built of semiconductor circuits.

The method according to claim 1 wherein said step of transforming the high-voltage input signal into the proportional current signal is implemented using a voltage to current conversion stage. The method according to claim 1 wherein in said step of transforming the high-voltage reference into the proportional current reference uses a voltage proportional to the high voltage supply.

The method according to claim 5 wherein said voltage proportional to the high voltage supply is realized with a resistive divider consisting of two resistors. The method according to claim 5 wherein said voltage proportional to the high voltage supply is realized with an equivalent resistive divider built of semiconductor circuits. The method according to claim 1 wherein in said step of transforming the high-voltage reference into the proportional current reference uses an absolute reference voltage. The method according to claim 8 wherein in said absolute reference voltage is implemented with the help of a separate internal semiconductor reference circuit.

The method according to claim 4 wherein said voltage to current conversion stage is implemented using a PMOS transistor, configured as a source follower working together with an NMOS transistor, which is employed as decoupling element for the low voltage domain. The method according to claim 4 wherein said gain stage is implemented using a PMOS transistor with extended drain, configured as a source follower working together with an NMOS transistor, which is employed as decoupling element for the low voltage domain.

The method according to claim 4 wherein said gain stage is implemented using a PMOS transistor, configured as a source follower working together with an NMOS transistor with extended drain, which is employed as decoupling element for the low voltage domain. The method according to claim 4 wherein said gain stage is implemented using a PMOS transistor with extended drain, configured as a source follower working together with an NMOS transistor with extended drain, which is employed as decoupling element for the low voltage domain.

A circuit, capable of comparing higher voltage signals, comprising:. The circuit according to claim 14 wherein said means for transforming the static high voltage supply level into the static currents is a resistor. The circuit according to claim 14 wherein said means for transforming the static high voltage supply level into the static currents is an equivalent resistor circuit built of semiconductor circuits. The circuit according to claim 14 wherein said means for transforming the high voltage reference input into the proportional current reference uses a voltage proportional to the high voltage supply.

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The circuit according to claim 17 wherein said voltage proportional to the high voltage supply is realized with a resistive divider consisting of two resistors. The circuit according to claim 17 wherein said voltage proportional to the high voltage supply is realized with an equivalent resistive divider circuit built of semiconductor circuits. The circuit according to claim 14 wherein said means for transforming the high-voltage reference into the proportional current reference uses an absolute reference voltage.

The circuit according to claim 20 wherein said absolute reference voltage is implemented with the help of a separate internal semiconductor reference circuit.


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The circuit according to claim 14 manufactured with the help of discrete active and passive components. The circuit according to claim 14 manufactured with the help of discrete components and integrated circuits. The circuit according to claim 14 manufactured in integrated circuit technology. The circuit according to claim 14 manufactured in monolithic integrated circuit technology. The circuit according to claim 14 manufactured in monolithic integrated CMOS technology. The circuit according to claim 14 wherein said means for comparing said current input signal and said reference current, designated as current comparator, is implemented in low voltage CMOS technology.

EP EPA1 en Comparator with high-voltage inputs in an extended CMOS process for higher voltage levels. USB1 en. EPA1 en.

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High-voltage devices for 0.5-μm standard CMOS technology

Marwick and A. Faramarzpour, M. Jamal Deen, S. Shirani, and Q. Electron Dev. Gersbach, R. Henderson, L. Grant, and E. Tosi, and F. Rochas, M. Gani, B. Furrer, P. Besse, R. Popovic, G. Ribordy, and N. Rochas, G. Ribordy, B. Besse, and R. Cova, A. Longoni, and A. Keil and H.

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Niclass and E. Sze, Physics of Semiconductor Devices, 2nd ed. Wiley, Citing articles from OSA journals and other participating publishers are listed here. Alert me when this article is cited. Click here to see a list of articles that cite this paper. Login or Create Account. Allow All Cookies. Optics Express Vol. Huang, J. Wu, J. Wang, C. Tsai, Y. Huang, D. Lin, "Single-photon avalanche diodes in 0. Express 25 , Accessible Open Access. Abstract We have designed and fabricated high-performance single-photon avalanche diodes SPADs by using 0.